Integrated circuit and method for minimizing clock skews

ABSTRACT

An integrated circuit interconnection comprising a transmission line having a low characteristic impedance, and including a first end and a second end. A driver is coupled to the first end of the transmission line, and the transmission line is terminated with a current sense amplifier having an input impedance corresponding to the characteristic impedance of the transmission line. A plurality of components selected from the group consisting of capacitive elements, inductive elements and a combination of capacitive and inductive elements are connected at spaced intervals to the transmission line between the first and second ends.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to minimizing clock skews bycurrent mode signals. More particularly, the present invention relatesto minimizing clock skews by current mode signals and changing apparentline lengths and transmission time delays.

[0003] 2. Discussion of the Related Art

[0004] Clock distribution is rapidly becoming one of the dominant designproblems due to the increasing die sizes and clock frequencies, even forclock frequencies below 1 GHz. Since the speed of integrated circuits isexpected to eventually reach above 10 GHZ, radically different on-chipinterconnection and clock distribution schemes will be needed.Consideration has been given to both wireless and optical clockdistribution. Wireless communication is described by K. Khong and K. O.Kenneth, “Characteristics of Integrated Dipole Antennas on Bulk, SOI andSOS Substrates for Wireless Communication”, Int. Interconnect TechnologyConf., San Francisco, Calif., June 1998, pp. 21-23. Also, U.S. Pat. No.5,812,708 discloses a method and apparatus for distributing an opticalclock in an integrated circuit.

[0005] The problem with current techniques is that most clockdistribution is achieved by voltage signals on RC lines and oncapacitance dominated lines. As shown in FIGS. 1A and 1B, the delay(t_(delay)) in the clocking step signal (V_(driver)(t)) is limited bythe RC time constant of the distribution line 20 if the line is highresistance polysilicon, or the RC time constant of the driver 22 outputresistance and line capacitance if low resistance metal lines are used.

[0006] The delay is represented by the equation:

D=Zdrv C _(T)+(Rl Cl)/2

[0007] where D=delay,

[0008] Zdrv=output impedance of the driver,

[0009] C_(T)=total capacitance seen by the driver,

[0010] R=resistance per unit length of the line of length, 1, and

[0011] C=capacitance per unit length of the line of length, 1.

[0012] Known techniques for minimizing clock skew are a tree typedistribution system with buffers to drive short lines of equal length,and having all buffers on the same die as described in U.S. Pat. Nos.5,586,307 and 4,860,322. Other known circuits include a daisy chainclock distribution network described in U.S. Pat. No. 5,546,023.

[0013] A circuit having lines of equal length is an H-tree distributionnetwork illustrated in FIG. 2 for a 4×4 array of cells to provide linesof equal length. The H-tree network has the property that the clocksignal is delayed by an equal amount for each sub-block because allblocks are equidistant from the clock source.

[0014] L. Maliniak in “DAC Attacks Designer Issues”, Electronic Design,vol. 43, p. 66, Jun. 12, 1995, describes other techniques for minimizingclock skew and delays including making some lines wider than others toincrease the capacitance to account for the shorter lengths. Further,U.S. Pat. No. 5,307,381 provides a technique which uses buffers ordrivers with various delays designed to compensate for different RC timeconstant delays and/or delays with can be varied by programming.

[0015] At higher clock speeds the inductance of even low resistancelines becomes important because the rise time on the waveformsapproaches the transit time down the line, or transmission line effectsbecome important. See A. Deutsch et al, “When are Transmission-LineEffects Important for On-Chip Interconnections?”, IEEE Trans. MicrowaveTheory and Techniques, vol. 45, no. 10, pp. 1836-18-46, 1997.

[0016] Unfortunately such transmission lines use large voltage swings orvoltage signaling, and cannot be terminated by a load resistor equal tothe characteristic low impedance of the lines. As a result, reflectionsand ringing occurs which corrupts the clock signal. Also, large voltagesignals and low impedance loads will result in excessive powerconsumption. See L. Maliniak, supra.

SUMMARY OF THE INVENTION

[0017] In accordance with the present invention, clock skew is avoidedor at least minimized by changing the apparent length of transmissionlines. The apparent length of a line is changed by adding capacitiveand/or inductive elements to change the propagation constant and delaytime of the line.

[0018] This is not the same technique as adding capacitance to RCdominated lines to change the time constant of the RC circuit. Addingcapacitance to RC dominated lines serves to reduce the rise time orresponse time and further degrade the signal quality.

[0019] The capacitive and/or inductive elements are added in accordancewith the present invention to change the propagation constant and delaytime in the propagation of the signal down the line. Changing the delaytime in this manner and by providing matched termination on the linecause the shape and quality of the signal to be maintained and onlydelays the signal in the time domain. In this manner the delay timealong lines of different lengths are made to match and clock skews areeliminated or at least minimized. Conversely desired delays can bepurposefully designed into the circuits to provide desired delay timesbetween clocks and/or signals.

[0020] In accordance with the present invention, there is provided anintegrated circuit interconnection comprising a transmission line havinga low characteristic impedance, and including a first end and a secondend. A driver is coupled to the first end of the transmission line, andthe transmission line is terminated with a current sense amplifierhaving an input impedance corresponding to the characteristic impedanceof the transmission line. A plurality of components selected from thegroup consisting of capacitive elements, inductive elements and acombination of capacitive and inductive elements are connected at spacedintervals to the transmission line between the first and second ends.

[0021] The combination of low characteristic impedance transmissionlines terminated in their characteristic impedance and current senseamplifiers which can discriminate against noise will result in welldefined signals with well defined delays.

[0022] As used herein, “low characteristic impedance” means less than100 ohms, and preferably less than 50 ohms.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1A is a graph plotting voltage against time to show the delayin the clocking step signal;

[0024]FIG. 1B is a schematic of a circuit showing the distribution on anR-C line of a clock signal emanating from an equivalent circuit of adriver having a voltage step signal output;

[0025]FIG. 2 is a schematic drawing of an H-tree distribution networkhaving transmission lines of equal length;

[0026]FIG. 3 shows an equivalent circuit of a transmission line withload equal to characteristic impedance;

[0027]FIG. 4 is a top view of a transmission line substrate havingcapacitive and/or inductive elements added thereto;

[0028]FIG. 5 is an equivalent circuit of the transmission line of FIG. 4showing noded capacitive elements added to change the signal delay;

[0029]FIG. 6A is a graph plotting voltage against time and showingsignal delay on a transmission line having matched termination;

[0030]FIG. 6B is another graph plotting voltage against time and showingthe signal on the R-C dominated distribution line wherein increasingcapacitance of line further degrades rise time of the signal;

[0031]FIG. 7 is schematic of a transmission line showing current signalclock distribution with variable delay by added capacitive elements inaccordance with the present invention;

[0032]FIG. 8 is a schematic diagram illustrating an embodiment of theinvention with a differential amplifier;

[0033]FIG. 9 is a schematic diagram illustrating an embodiment of theinvention with a pseudo differential amplifier circuit (or pseudodifferential latch or single ended receiver);

[0034]FIG. 10 is a schematic diagram illustrating an embodiment of theinvention with a pseudo differential current sense amplifier circuit;

[0035]FIG. 11A shows a schematic drawing of an embodiment of theinvention which includes a current sense amplifier with hysteresis; and

[0036]FIG. 11B is a graph illustrating the operation of the currentsense amplifier of FIG. 11A.

[0037] The above and other features and advantages of the invention willbe more readily understood from the following detailed description whichis provided in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

[0038] The following disclosure describes current mode signaling forclock distribution on low impedance transmission lines with matchedterminations. Ringing and reflections on these lines are minimized andthe delay on these lines is known and can be easily characterized. Theselines can be shielded lines, shielded differential lines and/or shieldedtwisted pairs to reduce noise. Current sense amplifiers with hysteresiscan be used to further discriminate against noise signals.

[0039] The combination of low impedance transmission lines terminated intheir characteristic impedance and current sense amplifiers which candiscriminate against noise will result in well defined signals with welldefined delays.

[0040]FIG. 3 shows an equivalent circuit of a transmission line 30between a load 32 and a driver 31. The load 32 is equal to thecharacteristic impedance. The inductor symbols 34 in FIG. 3 representinductance per unit length of the transmission line 30, and thecapacitor symbols 36 represent capacitance per unit length of the line30. The delay on the line 30 is characterized by the propagationconstant of the line in accordance with:

B=j w (LC)^(1/2)

[0041] where B=propagation constant of line,

[0042] L=inductance of line per unit length, and

[0043] C=capacitance of line per unit length.

[0044] The transit time delay down the line of length is:

t _(d) =l/v

[0045] where t_(d)=transit time delay

[0046] l=length of line, and

[0047] v=velocity of the signal=l/(LC)^(1/2).

[0048] Clock skew could be avoided by having all lines of the samelength. However, this would result in excessively long lines since alllines must be as long as the longest one required. It would also resultin little flexibility in circuit designs.

[0049] With reference to FIG. 4, the present invention provides forchanging the apparent length of a transmission line 44 in a substrate 40by adding capacitive and/or inductive elements 42 to alter thepropagation constant and delay time of the line 44. FIG. 5 is anequivalent circuit of the transmission line 44 of FIG. 4 showing nodedcapacitive elements 42A added to change the signal delay. As discussedabove with reference to FIG. 3, the inductor symbols 46 in FIG. 4represent inductance per unit length of the transmission line 44, andthe capacitor symbols 48 represent capacitance per unit length of theline 44.

[0050] The addition of capacitive and/or inductive elements 42, asdescribed with reference to FIGS. 4 and 5, is not the same technique asadding capacitance to RC dominated lines to change the time constant ofthe RC circuit. As shown in FIG. 6B, adding capacitance to a RCdominated line reduces the rise time or response time and furtherdegrades the signal quality.

[0051] However, when the capacitive and/or inductive elements are addedin accordance with the invention the propagation constant and delay timein propagation of the signal down the line are changed. Changing thedelay time in this manner and also providing matched termination on theline function to preserve the shape and quality of the signal and onlydelays the signal in the time domain as shown in FIG. 6A. The delay timealong lines of different lengths is thereby made to match and clockskews are eliminated or at least minimized. Also, desired delays can bedesigned into the circuits to provide planned delay times between clocksand/or signals.

[0052] With reference to FIG. 7, there is shown a schematic drawing of atransmission line 70 between a driver 72 and a current sense amplifier74. A plurality of interconnection (transmission) lines 76 are providedalong the transmission line 70. Current mode signaling is used on lineswhich normally have a low characteristic impedance on integratedcircuits. These lines are terminated in their characteristic impedanceto reduce ringing and reflections. A plurality of capacitive elements 78are connected at spaced intervals to the transmission line 70 to varyclock signal delay times in accordance with the present invention.

[0053] The illustration of FIG. 7 shows the capacitive elements 78 asextensions of the interconnection metal wiring. The desired capacitanceof elements 42 (FIG. 4), 42A (FIG. 5) and 78 (FIG. 7) can also beprovided by the gate capacitances of field effect transistors (FETs)where the FETs are used as capacitors. Specialized capacitive structuressuch as metal-metal, metal-polysilicon or polysilicon-polysiliconcapacitors are also suitable.

[0054] As noted above with reference to at least FIG. 4, clock signaldelay times can also be varied by adding inductive elements in series tothe line 44. If inductors are introduced into the series path they canbe implemented as spiral inductors. Also, the self inductance of theline 44 can be increased by the deposition of materials with a highermagnetic permeability.

[0055] With reference to FIG. 8, there is shown a differential receiverdesigned for current signaling in order to better impedance match highspeed low impedance transmission lines. Low impedance transmission linessuch as those which exist on CMOS integrated circuits are more amenableto current signaling over longer transmission lines. The receiveremploys feedback to decrease the input impedance of the receiver. Thereceiver of the present invention can match the low impedance oftransmission lines while keeping the sizes of devices small and thepower dissipation low.

[0056]FIG. 8 illustrates a pair of cross coupled complementary metaloxide semiconductor (CMOS) amplifiers, A1 and A2 for coupling withinterconnection (transmission) lines 152A, 152B. Each amplifier, A1 andA2, includes a first transistor, Q1 and Q2 respectively, of a firstconductivity type. Each first transistor Q1 and Q2 includes a sourceregion, 107A and 107B, respectively, a drain region, 108A and 108B, anda gate, 109A and 109B, opposing a body region 110A and 110B. Eachamplifier, A1 and A2, includes a second transistor Q3 and Q4 of a secondconductivity type. Each second transistor Q3 and Q4 includes a sourceregion, 114A and 114B, respectively, a drain region, 116A and 116B and agate, 118A and 118B, opposing a body region 120A and 120B. In oneembodiment, each first transistor, Q1 and Q2, of the first conductivitytype includes an n-channel metal-oxide semiconductor (NMOS) transistor.In this embodiment, each second transistor, Q3 and Q4, of the secondconductivity type includes a p-channel metal-oxide semiconductor (PMOS)transistor.

[0057] A plurality of interconnection (transmission) lines 76A, 76B areprovided along transmission lines 152A, 152B. A plurality of capacitiveelements 78A, 78B are connected at spaced intervals along thetransmission lines 152A, 152B to vary clock signal delay times asdescribed above with reference to FIG. 7.

[0058] As shown in FIG. 8, each amplifier in the pair of cross coupledamplifiers A1 and A2 includes a signal input node, 122A and 122B,coupled to the source region 107A and 107B for the first transistor Q1and Q2. A signal output node 124A and 124B is coupled to the drainregions 108A and 108B of the first transistors Q1 and Q2 as well as tothe drain regions 116A and 116B of each second transistor Q3 and Q4.

[0059] Further, a third transistor, Q5 and Q6, respectively, is includedin each of the amplifiers A1 and A2. Each third transistor, Q5 and Q6,includes a source region, 130A and 130B respectively, a drain region,132A and 132B, and a gate, 134A and 134B, opposing a body region 136Aand 136B. The gate, 134A and 134B, of each third transistor, Q5 and Q6,is coupled to the signal input node, 122A and 122B, for each amplifierin the pair of cross coupled amplifiers A1 and A2. The drain region 132Aand 132B for each third transistor Q5 and Q6 is coupled to a positivevoltage supply, 138A and 138B. The source region 130A and 130B for eachthird transistor Q5 and Q6 is coupled to a lower potential, 140A and140B. The drain region 132A and 132B for each third transistor Q5 and Q6is additionally coupled to the gate 109A and 109B for each firsttransistor Q1 and Q2.

[0060] In the embodiment shown in FIG. 8, each amplifier, A1 and A2,includes a fourth transistor, Q7 and Q8 respectively, of the firstconductivity type. Each fourth transistor Q7 and Q8 includes a sourceregion, 144A and 144B respectively, a drain region, 146A and 146B, and agate, 148A and 148B, opposing a body region 150A and 150B. The drainregion 146A and 146B for each fourth transistor, Q7 and Q8, is coupledto the signal input node, 122A and 122B, for each amplifier in the pairof cross coupled amplifiers A1 and A2.

[0061] In one embodiment of the circuit of FIG. 8, the signal outputnode 124A for first amplifier A1 is cross coupled to the gates 118B and148B for the second transistor Q4 and the fourth transistor Q8 of thesecond amplifier A2. Similarly, the signal output node 124B for secondamplifier A2 is cross coupled to the gates 118A and 148A for the secondtransistor Q3 and the fourth transistor Q7 of the first amplifier A1.

[0062] Each signal input node, 122A and 122B, for each amplifier in thepair of cross coupled amplifiers A1 and A2 is coupled to an inputtransmission line, 152A and 152B respectively, which has a length of atleast 500 micrometers (μm), but may have a length of at least 1000micrometers (μm). In one embodiment, each signal input node, 122A and122B, is coupled to the input transmission line 152A and 152B which hasa characteristic impedance (Zo) of less than 50 Ohms. In anotherembodiment, each signal input node, 122A and 122B, in the pair of crosscoupled amplifiers A1 and A2 is coupled to an input transmission line152A and 152B which has a characteristic impedance (Zo) of less than 75Ohms. Preferably, each signal input node, 122A and 122B has an inputimpedance (Zin) which matches the characteristic impedance (Zo) of thetransmission line 152A and 152B.

[0063]FIG. 9 shows another embodiment of the invention having a“pseudo-differential” amplifier 300. The amplifier 300 is coupled tointerconnection (transmission) lines 352. A plurality of interconnection(transmission) lines 376 are provided along the transmission line 352. Aplurality of capacitive elements 378 are connected at spaced intervalsalong the transmission line 352 to vary clock signal delay times asdescribed above with reference to FIG. 7.

[0064] As used herein, “pseudo-differential amplifier” means anamplifier circuit wherein a single transmission line interconnection isused, and one input of the voltage sense amplifier is driven with areference potential. The pseudo differiental amplifier includes a singlesignal input node coupled to the single transmission lineinterconnections, and a pair of signal output nodes, whereby theamplifier is able to convert a single ended input current received atthe single signal input node into a differential input signal.

[0065] Unfortunately, achieving high data rates is difficult with priorart circuits having single-ended or unbalanced signal transmission linesat high frequencies because of large amount of noise is generated in theinterconnection system including crosstalk and radiation in backplanes,connectors and cables. The amplifier of FIG. 9 has a single signal inputnode which is coupled to a source region for one of the transistors inthe pair of cross coupled transistors and to a current mirror such thatthe pseudo differential amplifier is able to convert a single endedinput current received at the single signal input node into adifferential input signal.

[0066]FIG. 9 is a schematic diagram which illustrates a pseudodifferential amplifier circuit (or pseudo differential latch, or singleended receiver) 300. FIG. 9 illustrates a pair of cross coupledamplifiers, A1 and A2. The pair of cross coupled amplifiers, A1 and A2,comprise two cross coupled inverters. Each amplifier, A1 and A2,includes a first transistor, Q1 and Q2, respectively, of a firstconductivity type. Each first transistor Q1 and Q2 includes a sourceregion, 307A and 307B, respectively, a drain region, 308A and 308B, anda gate, 309A and 309B, opposing a body region 310A and 310B. Eachamplifier, A1 and A2, includes a second transistor Q3 and Q4 of a secondconductivity type. Each second transistor Q3 and Q4 includes a sourceregion, 314A and 314B, respectively, a drain region, 316A and 316B, anda gate, 318A and 318B, opposing a body region 320A and 320B. In anembodiment, each first transistor, Q1 and Q2, of the first conductivitytype includes a metal oxide semiconductor field effect transistor(MOSFET). In another embodiment, each first transistor, Q1 and Q2, of afirst conductivity type includes an n-channel metal-oxide semiconductor(NMOS) transistor. In one embodiment, each second transistor, Q3 and Q4,of the second conductivity type includes a metal oxide semiconductorfield effect transistor (MOSFET). Alternatively, each second transistor,Q3 and Q4, of the second conductivity type includes a p-channelmetal-oxide semiconductor (PMOS) transistor. The NMOS and PMOStransistors are fabricated according to a complementary metal oxidesemiconductor (CMOS) process technology.

[0067] In FIG. 9, the single signal input node 322 is coupled to thesource region, 307A or 307B, for one of the first transistors, Q1 andQ2, in the pair of cross coupled amplifiers A1 and A2. By way ofillustration, FIG. 9 shows the single signal input node 322 coupled tothe source region 307A of transistor Q1. A signal output node 324A and324B in each inverter A1 and A2 is coupled to the drain regions 308A and308B of the first transistors Q1 and Q2 as well as to the drain regions316A and 316B of each second transistor Q3 and Q4. The signal outputnodes 324A and 324B in each one of the cross coupled inverters A1 and A2is further coupled to the gates of the first and the second transistorsin the other inverter. Hence, signal output node 324A is coupled togates 309B and 318B of inverter A2, and signal output node 324B iscoupled to gate 309A and 318A of inverter A1. In one embodiment, thesignal output nodes 324A and 324B are coupled respectively to a pair ofoutput transmission lines 354A and 354B. The single signal input node322 is additionally coupled to a current mirror MI. In one embodiment,the transmission line 352 which has a characteristic impedance (Zo) ofless than 50 Ohms is coupled to the signal input node 322.

[0068] In FIG. 9, a third transistor, Q5 and Q6 respectively, of a firstconductivity type is coupled to each amplifier, A1 and A2. Each thirdtransistor includes a source region, 344A and 344B respectively, a drainregion, 346A and 346B, and a gate, 348A and 348B, opposing a body region350A and 350B. The drain region 346A and 346B for each third transistor,Q5 and Q6, is coupled to the source region, 307A and 307B, for eachfirst transistor Q1 and Q2 in the pair of cross coupled amplifiers A1and A2. The single signal input node 322 additionally couples to thegate, 348A and 348B, for each third transistor Q5 and Q6. In oneembodiment, each third transistor, Q5 and Q6, of a first conductivitytype comprise a second pair of MOSFETs of a first conductivity type forthe pseudo differential amplifier circuit 300. In this embodiment, thesecond pair of MOSFETs of first conductivity type includes a pair ofNMOS transistors Q5 and Q6. Also in this embodiment, the pair of NMOStransistors Q5 and Q6 are part of the current mirror M1. Here, a drainregion, 346A and 346B, for each one of the pair of NMOS transistors Q5and Q6 in the current mirror M1 is coupled to a source region, 307A and307B respectively, for each NMOS transistor Q1 and Q2 in the pair ofcross coupled inverters A1 and A2. The single signal input node 322 iscoupled a gate on each one of the pair of NMOS transistors Q5 and Q6 inthe current mirror M1.

[0069] The pseudo differential amplifier circuit of FIG. 9 eliminates aspacial problem in the prior art which requires two input signals byfacilitating differential sensing capability using a single endedreceiver. This solution is achieved as follows. With reference to FIG.9, the current mirror M1 converts a single ended input current receivedat the single signal input node 322 into a differential input signal.

[0070] For example, output node 324A and 324B are precharged to avoltage potential prior to the sensing operation. Next, a current signalis input from input transmission line 352 into single signal input node322. When the current signal arrives at single signal input node 322 aportion of the signal flows into the gates 348A and 348B for transistorsQ5 and Q6 serving to turn “on” these transistors. This createsconduction between source region 344A and drain region 346A oftransistor Q5 as well as between source region 344B and drain region346B of transistor Q6. If the input current signal flows into the drainregion 346A of transistor Q5 then some current will also flow into thesource region 307A of transistor Q1. The current flowing into the sourceregion 307A of transistor Q1 will decrease the current flowing out ofthe drain region 316A of transistor Q3 and out of the source region 307Aof transistor Q1. The precharged voltage potential, or node voltage V1,at output node 324A will subsequently increase which serves to turntransistor Q2 on and turn off transistor Q4. At the same time, anincrease in the conduction between source region 344A and drain region346A in transistor Q5 will cause the potential, or node voltage V3, atthe signal input node 322 to increase which in turn increases thevoltage on gate 348B of transistor Q6. An increasing gate voltage ontransistor Q6 will further turn on transistor Q6 such that transistor Q6conducts more current through transistor Q6 between drain region 346Band source region 344B. This increase in conduction through transistorQ6 will tend to cause the current flowing out of the source region 307Bof transistor Q2 to increase. The increased conduction throughtransistors Q2 and Q6 tend to pull signal output node 324B to groundreducing the node voltage V2 at signal output node 324B. As the nodevoltage V2 of signal output node 324B is reduced, transistor Q3 isfurther turned on. In this manner, the single ended receiver, or pseudodifferential amplifier circuit 300 operates in a differential amplifierfashion. The single ended current signal which was input fromtransmission line 352 into signal input 322 is thus converted into adifferential current signal in that the source current at source region307A of transistor Q1 tends to decrease and the source current at sourceregion 307B of transistor Q2 tends to increase. As a result, the pseudodifferential amplifier of FIG. 9 produces the same effect that a fullydifferential signal would have on a conventional differential currentsense amplifier.

[0071] Also, the pseudo differential amplifier avoids the necessityhaving two transmission lines as in a conventional differential currentsense amplifier. The pseudo differential amplifier circuit 300 can latcha voltage output signal on the pair of signal output nodes, 324A and324B, and the pair of output transmission lines 354A and 354B when asingle sided current signal of 2.0 mA or less is received at the singlesignal input node 322. The pseudo differential amplifier circuit 300 canlatch this voltage output signal to the pair of signal output nodes,324A and 324B in less than 300 nanoseconds (ns). This is a very rapidresponse time and is on a par with that provided by conventionaldifferential current sense amplifiers. Further, the pseudo differentialamplifier circuit described here is fully capable of fabrication in astreamlined CMOS process.

[0072]FIG. 10 is a schematic diagram illustrating another pseudodifferential current sense amplifier circuit, or single ended amplifier400. The amplifier 400 is coupled to transmission line 452. A pluralityof interconnection (transmission) lines 376A are provided along thetransmission line 452. A plurality of capacitive elements 378A areconnected at spaced intervals along the transmission line 452 to varyclock signal delay times as described above with reference to FIG. 7.

[0073] The pseudo differential amplifier circuit 400 of FIG. 10 isuseful in amplifier roles which do not require a latching action. FIG.10 illustrates a pair of cross coupled amplifiers, B1 and B2. Eachamplifier, B1 and B2, includes a first transistor, Z1 and Z2,respectively, of a first conductivity type. Each first transistor Z1 andZ2 includes a source region, 407A and 407B, respectively, a drainregion, 408A and 408B, and a gate, 409A and 409B, opposing a body region410A and 410B. Each amplifier, B1 and B2, includes a load resistor Z3and Z4. Each load resistor Z3 and Z4 is coupled to the drain region foreach one of the first transistors Z1 and Z2 respectively in the pair ofcross coupled amplifiers B1 and B2. In one embodiment, each firsttransistor, Z1 and Z2, of a first conductivity type includes a pair ofmetal oxide semiconductor field effect transistors (MOSFET).Alternatively, each first transistor, Z1 and Z2, of the firstconductivity type includes an n-channel metal-oxide semiconductor (NMOS)transistor.

[0074] In FIG. 10, a single signal input node 422 is coupled to thesource region, 407A or 407B of one of the first transistors, Z1 and Z2,in the pair of cross coupled amplifiers A1 and A2. By way ofillustration, FIG. 10 shows the single signal input node 422 coupled tothe source region 407A of transistor Z1. A signal output node 424A and424B in each amplifier in the pair of cross coupled amplifiers B1 and B2is coupled to the drain regions 408A and 408B of the first transistorsZ1 and Z2 as well as to the load resistors Z3 and Z4. The signal outputnodes 424A and 424B in each one of the cross coupled amplifiers B1 andB2 is further coupled to the gate of the first transistor in the otheramplifier. Hence, signal output node 424A is coupled to gate 409B ofamplifier B2, and signal output node 424B is coupled to gate 409A ofamplifier B1. In one embodiment, the signal output nodes 424A and 424Bare coupled respectively to a pair of output transmission lines 454A and454B. The single signal input node 422 is additionally coupled to acurrent mirror X1. In one embodiment, the transmission line 452 whichhas a characteristic impedance (Zo) of less than 50 Ohms is coupled tothe signal input node 422.

[0075] In FIG. 10, a second transistor, Z5 and Z6 respectively, of afirst conductivity type is coupled to each amplifier, B1 and B2. Eachsecond transistor Z5 and Z6 includes a source region, 444A and 444Brespectively, a drain region, 446A and 446B, and a gate, 448A and 448B,opposing a body region 450A and 450B. The drain region 446A and 446B foreach second transistor, Z5 and Z6, is coupled to the source region, 407Aand 407B, for each first transistor Z1 and Z2 in the pair of crosscoupled amplifiers A1 and A2. The single signal input node 422additionally couples to the gate, 448A and 448B, for each secondtransistor Z5 and Z6. Alternatively, each second transistor, Z5 and Z6,of a first conductivity type comprise a second pair of MOSFETs of afirst conductivity type for the pseudo differential amplifier circuit400. In this embodiment, the second pair of MOSFETs of a firstconductivity type includes a pair of NMOS transistors Z5 and Z6. Also inthis embodiment, the pair of NMOS transistors Z5 and Z6 are part of thecurrent mirror X1. Here, a drain region, 446A and 446B, for each one ofthe pair of NMOS transistors Z5 and Z6 in the current mirror X1 iscoupled to a source region, 407A and 407B respectively, for each NMOStransistor Z1 and Z2 in the pair of cross coupled amplifiers B1 and B2.The single signal input node 422 is coupled to a gate on each one of thepair of NMOS transistors Z5 and Z6 in the current mirror X1.

[0076] The operation of the pseudo differential amplifier circuit 400 inFIG. 10 is analogous to the operation of the pseudo differentialamplifier circuit 300 in FIG. 9. The pseudo differential amplifiercircuit 400 conserves chip surface area by facilitating differentialsensing capability using a single ended receiver. In the pseudodifferential amplifier circuit 400 shown in FIG. 10 the amplifier actionof the upper transistors Q3 and Q4 shown in FIG. 9 have been replaced byload resistors Z3 and Z4. The use of load resistors Z3 and Z4 ratherthan active transistors Q3 and Q4 as load devices results in a lowergain, slower response and more input current being required to achievelatching action if such is desired. Nonetheless, the pseudo differentialamplifier circuit 400 is very well suited to and responsive in anamplifying signal detection role. The pseudo differential amplifiercircuit 400 can provide a differential voltage signal to the pair ofsignal output nodes 424A and 424B and the pair of output transmissionlines 454A and 454B when a single ended input current of less than 1.0mA is received at the single signal input node 422. The pseudodifferential amplifier circuit 400 can provide the differential voltagesignal to the pair of signal output nodes in less than 300 nanoseconds(ns). This is a very rapid response time and is on par with thatprovided by conventional differential current sense amplifiers. Thepseudo differential amplifier circuit 400 is fully capable offabrication in a streamlined CMOS process. Further, since the pseudodifferential amplifier circuit 400 operates with only a single signalinput node and single input transmission line, precious chip surfacearea is conserved.

[0077] With reference to FIGS. 11A and 11B, there is shown a currentsense amplifier (or current comparator) 800 with hysteresis fabricatedaccording to CMOS process technology. The amplifier 800 is coupled to atransmission line 852. A plurality of interconnection (transmission)lines 876 are provided along the transmission line 852. A plurality ofcapacitive elements 878 are connected at spaced intervals along thetransmission line 852 to vary clock signal delay times as describedabove with reference to FIG. 7.

[0078] The introduction of hysteresis into the current sense amplifiersand/or receivers will allow them to discriminate against noisetransients since the output will not change states unless the signalbecomes more positive than a high trip point, or more negative than alow trip point.

[0079] The current sense amplifier 800 includes a first amplifier 810,and a second amplifier 820. Each amplifier, 810 and 820, includes afirst transistor of a first conductivity type, M1 and M2 respectively.Each amplifier, 810 and 820, includes a second transistor of a secondconductivity type, M3 and M4 respectively. The first transistor of afirst conductivity type, M1 and M2, includes an n-channel metal oxidesemiconductor (NMOS) transistor, M1 and M2. In this embodiment, thesecond transistor of a second conductivity type, M3 and M4, includes ap-channel metal oxide semiconductor (PMOS) transistor, M3 and M4.Transistors M1 and M2 are driven by a gate potential at node 7. Eachamplifier, 810 and 820, includes a current sink, shown in FIG. 11A astransistors M5 and M6 which are driven by a gate potential at node 6.The first and second transistors, M1 and M3, of the first amplifier 810are coupled at a drain region, 821 and 822 respectively, to node 1.

[0080] Node 1 couples the drain region, 821 and 822, for the first andthe second transistor, M1 and M3, in the first amplifier 810 to gates,840 and 841, of the second transistor, M3 and M4, in the first and thesecond amplifier 810 and 820. The first and second transistors, M2 andM4, of the second amplifier 820 are coupled at a drain region, 823 and824 respectively. In the embodiment shown in FIG. 11A, a signal outputnode 2 is coupled to the drain region, 823 and 824, of the first and thesecond transistor, M2 and M4, in the second amplifier 820. In analternative embodiment, the signal output node 2 can be coupled to thedrain region, 821 and 822, of the first and the second transistor, M1and M3, in the first amplifier 810. As shown in FIG. 11A the signaloutput node is further coupled to a gate 880 of a third transistor M8.In one embodiment, the third transistor M8 is an n-channel metal oxidesemiconductor (NMOS) transistor M8. Each amplifier, 810 and 820,includes a signal input node, 5 and 4 respectively, which is coupled toa source region, 825 and 826, of the first transistor, M1 and M2.

[0081] A source region, 827 and 828, for the second transistor, M3 andM4 respectively, in the first and second amplifier, 810 and 820, iscoupled to a voltage supply Vdd at node 3. In one embodiment, a drainregion 836 of the third transistor M8 is coupled to a source region 828of the second transistor M4 in the second amplifier 820. In thisembodiment, a source region 837 of the third transistor M8 is coupled tothe signal input node 4 of the second amplifier 820. The signal inputnode 5 of the first amplifier 810 receives an input current, I1, and thesignal input node 4 of the second amplifier 820 receives a referencecurrent, I2.

[0082]FIG. 11B is an I-V graph illustrating the operation of the currentsense amplifier circuit 800 shown in FIG. 11A. The operation of thecurrent sense amplifier circuit 800 is explained by reference to FIGS.11A and 11B. The third transistor M8 introduces a controlled hysteresisinto the current sense amplifier 800 of FIG. 11A. Beginning at the lefthand side of the graph, FIG. 11B illustrates the output voltage, V2, ata high state output voltage. The high state output voltage, V2, turns onthird transistor M8 which then drives an input current, IM8, into node4. In other words, the third transistor M8 provides an input current,IM8, into node 4 which acts in conjunction with the reference currentI2. The single ended input current, I1, must overcome this combinationof the reference, or differential current, I2, and the input current,IM8, before the output voltage, V2, can change states. At this point,the switching action of the output voltage, V2, of the current senseamplifier 800 is given by V2=−Zv(I1−(I2+IM8)). The value of(I1−(I2+IM8)) must become non zero or positive for the output to switch,or go to the second state, e.g. low state. Due to the input current IM8,I1 will not “trip” the state of the current sense amplifier 800 until I1exceeds a certain positive current value, i.e. a high trip point, shownat 850 in FIG. 11B. The size and doping levels of the third transistorM8 can be varied to provide a set magnitude of input current, IM8, intonode 4. In this manner, the circuit design of the current senseamplifier 800 can be manipulated to introduce a range of hysteresis forpositive input current, I1, values into the current sense amplifier 800.The set hysteresis introduced, by the addition of the third transistorM8, allows the current sense amplifier 800 to discriminate against smalltransient noise values which would otherwise cause the current senseamplifier to switch states prematurely and provide an inaccurate outputvoltage, V2.

[0083] In reverse operation, the single ended input current, I1, isdecreased from a higher positive value, e.g. above trip point value 850.As shown in FIG. 11B, while the input current, I1, is above trip point850 the output voltage, V2, will be at a low state output voltage. Inthis low state, the voltage potential applied to gate 880 of the thirdtransistor M8 will not turn “on” transistor M8. Thus, the thirdtransistor M8 is effectively removed from the current sense amplifiercircuit 800. In the embodiment of FIGS. 11A and 11B, node 4 will onlysee a reference current, I2, here held at zero amperes. In other words,the third transistor is not providing any input current, IM8, into node4. In reverse operation, the single ended input current, I1, must againupset the balance of the current sense amplifier 800, but in theopposite direction, e.g. the input current, I1, must overcome thereference or differential current, 12, of zero amperes before the outputvoltage, V2, will again change states. At this point, the outputvoltage, V2, of the current sense amplifier 800 is given byV2=−Zv(II−I2). In this reverse direction, (I1−I2) must become negativefor the output voltage, V2, to switch back, or return to the high stateoutput voltage. I1 will not “trip” the state of the current senseamplifier 800 until I1 passes below a second current value, i.e. a lowtrip point, shown at 860 in FIG. 11B. In the embodiment shown in FIGS.11A and 11B, the output voltage, V2, will not change states until I1 hasreached zero. Other high and low trip points can be achieved by varyingthe amount of hysteresis introduced by the third transistor M8 and/or byvarying the differential/reference signal 12 of the current senseamplifier 800.

[0084] Although the present invention has been described with referenceto preferred embodiments, it is to be understood that modifications andvariations may be made without departing from the spirit and scope ofthis invention, as those skilled in the art will readily understand. Allsuch modifications and variations are considered to be part of theinvention. Accordingly, the invention is not limited by the foregoingdescription, but is only limited by the scope of the appended claims.

What is claimed is:
 1. An integrated circuit interconnection comprising:a transmission line having a low characteristic impedance, saidtransmission line including a first end and a second end; a drivercoupled to the first end of said transmission line; a termination at thesecond end of said transmission line having an impedance correspondingto the characteristic impedance of said transmission line;* and aplurality of components selected from the group consisting of capacitiveelements, inductive elements and a combination of capacitive andinductive elements, said components being connected at spaced intervalsto said transmission line between said first and second ends.
 2. Theintegrated circuit interconnection of claim 1 wherein said componentschange the propagation constant and delay time of said transmissionline.
 3. The integrated circuit interconnection of claim 1 wherein saidcomponents are a plurality of capacitive elements.
 4. The integratedcircuit interconnection of claim 1 wherein said components are aplurality of inductive elements.
 5. The integrated circuitinterconnection of claim 1 wherein said components are a combination ofcapacitive and inductive elements.
 6. The integrated circuitinterconnection of claim 1 wherein said transmission line has acharacteristic impedance of less than 50 Ohms.
 7. The integrated circuitinterconnection of claim 1 wherein a current sense amplifier is coupledto the second end of the transmission line.
 8. The integrated circuitinterconnection of claim 1 wherein a plurality of interconnection linesare connected to said transmission line.
 9. The integrated circuitinterconnection of claim 3 wherein said capacitive elements are selectedfrom the group consisting of metal-metal, metal-polysilicon andpolysilicon-polysilicon capacitors.
 10. The integrated circuitinterconnection of claim 1 wherein said capacitive elements are gatecapacitances of field effect transistors used as capacitors.
 11. Theintegrated circuit interconnection of claim 1 wherein said inductiveelements are spiral inductors serially implanted in said transmissionline.
 12. The integrated circuit interconnection of claim 1 wherein saidinductive elements are formed by depositing material with a highermagnetic permeability on said transmission line for increasing selfinductance of said transmission line.
 13. The integrated circuitinterconnection of claim 1 wherein said termination is formed incomplementary metal-oxide semiconductor (CMOS) technology on the secondend of said transmission line.
 14. The integrated circuitinterconnection of claim 7 wherein said current sense amplifier whichhas an input impedance of less than 50 Ohms.
 15. The integrated circuitinterconnection of claim 1 wherein and a differential receiver iscoupled to the second end of the transmission line.
 16. The integratedcircuit interconnection of claim 1 wherein an amplifier circuitcomprising a pair of cross coupled CMOS amplifiers is coupled to thesecond end of said transmission line.
 17. The integrated circuitinterconnection of claim 16 wherein each amplifier comprising: a firsttransistor of a first conductivity type having a source region, a drainregion, and a gate opposing a body region; a second transistor of asecond conductivity type having a source region, a drain region, and agate opposing a body region; a signal input node coupled to the sourceregion for the first transistor; a signal output node coupled to thedrain regions for the first transistor and the second transistor; and athird transistor of a first conductivity type having a source region, adrain region, and a gate opposing a body region, wherein the signalinput node is coupled to the gate of the third transistor, wherein thedrain region is coupled to a positive voltage supply and the sourceregion is coupled to a lower voltage potential, and wherein the drainregion is coupled to the gate of the first transistor; said second endof said transmission line being coupled to the signal input of a firstone of the pair of cross coupled CMOS amplifiers; and a secondtransmission line coupled to the signal input of a second one of thepair of cross coupled CMOS amplifiers.
 18. The integrated circuitinterconnection of claim 17, wherein the first transistor of a firstconductivity type includes an n-channel metal-oxide semiconductor (NMOS)transistor, and wherein the second transistor of a second conductivitytype includes a p-channel metal-oxide semiconductor (PMOS) transistor.19. The integrated circuit interconnection of claim 18, wherein eachamplifier in the amplifier circuit includes a fourth transistor of afirst conductivity type having a source region, a drain region, and agate opposing a body region, wherein the drain region is coupled to thesource region for the first transistor.
 20. The integrated circuitinterconnection of claim 19, wherein the signal output node for eachamplifier is cross coupled to the gate of the second transistor and thefourth transistor on the other amplifier.
 21. The integrated circuitinterconnection of claim 16 wherein the signal input node for eachamplifier is coupled to a transmission line which has a length of atleast 1000 micrometers.
 22. The integrated circuit interconnection ofclaim 16 wherein the signal input node for each amplifier is coupled toa transmission line which has a length of at least 500 micrometers. 23.The integrated circuit interconnection of claim 1 wherein an amplifiercircuit is coupled to the second end of said transmission line.
 24. Theintegrated circuit interconnection of claim 13 wherein said amplifiercircuit comprises: a pair of cross coupled transistors; a pair of outputtransmission lines, wherein each one of the pair of output transmissionlines is coupled to a drain region on each one of the pair of crosscoupled transistors; and a single signal input node coupled to a sourceregion for one of the pair of cross coupled transistors, wherein theamplifier circuit is able to provide a differential voltage signal tothe pair of output transmission lines when a single ended input currentof less than 1.0 mA is received at the single signal input node.
 25. Theintegrated circuit interconnection of claim 24, wherein each one of thepair of output transmission lines coupled to the drain region on eachone of the pair of cross coupled transistors is further coupled to agate for the other transistor in the pair of cross coupled transistors.26. The integrated circuit interconnection of claim 25, wherein eachtransistor in the pair of cross coupled transistors an n-channel metaloxide semiconductor (NMOS) transistor.
 27. The integrated circuitinterconnection of claim 24, wherein the single signal input node iscoupled to a current mirror.
 28. The integrated circuit interconnectionof claim 1 wherein a pseudo differential amplifier circuit is coupled tothe second end of said transmission line.
 29. The integrated circuitinterconnection of claim 28 wherein said pseudo differential amplifiercircuit comprises: a first pair of metal oxide semiconductor fieldeffect transistors (MOSFETs), wherein the first pair of MOSFETS arecross coupled; a pair of load resistors, wherein each load resistor is,coupled to a drain region for each MOSFET in the first pair of MOSFETs;a pair of signal output nodes, wherein each one of the pair of signaloutput nodes is coupled to the drain region for each MOSFET in the firstpair of MOSFETs; a single signal input node coupled to a source regionfor one of the MOSFETs in the first pair of MOSFETs; and a second pairof MOSFETs, wherein a drain region for each MOSFET in the second pair ofMOSFETs is coupled to a source region of for each MOSFET in the firstpair of MOSFETs, and wherein the signal input node is coupled to a gatefor each of the second pair of MOSFETs.
 30. The integrated circuitinterconnection of claim 29, wherein the pseudo differential amplifieris able to provide a different voltage signal to the pair of signaloutput nodes when current signal of 0.5 mA or less is received at thesingle signal input node.
 31. The integrated circuit interconnection ofclaim 29 wherein the first pair of MOSFETs includes a first pair ofn-channel metal oxide semiconductor (NMOS) transistors.
 32. Theintegrated circuit interconnection of claim 29, wherein the second pairof MOSFETs includes a second pair of n-channel metal oxide semiconductor(NMOS) transistors.
 33. The integrated circuit interconnection of claim29, wherein said transmission line has a characteristic impedance ofless than 50 Ohms.
 34. The integrated circuit interconnection of claim29, wherein the drain region for each MOSFET in the first pair ofMOSFETs is coupled to a gate of the other MOSFET in the first pair ofMOSFETs.
 35. The integrated circuit interconnection of claim 1 wherein asingle ended amplifier circuit is coupled to the second end of saidtransmission line.
 36. The integrated circuit interconnection of claim35 wherein said single ended amplifier circuit comprises: a pair ofcross coupled amplifiers, wherein each amplifier comprises: a loadresistor; a first transistor having a source region, a drain regioncoupled to the load resistor, and a gate opposing a body region; asignal output node coupled to the drain region for the first transistor;and a second transistor having a source region, a drain region, and agate opposing a body region, wherein the drain region of the secondtransistor is coupled to the source region of the first transistor; anda signal input node coupled to the source region for the firsttransistor in one of the cross coupled amplifiers, wherein the signalinput node is further coupled to the gate in each second transistor. 37.The integrated circuit interconnection of claim 36, wherein the singleended amplifier provides an amplified output signal to the output nodesin the pair of cross coupled amplifiers when a 0.5 mA single ended inputcurrent is received at the single signal input node.
 38. The integratedcircuit interconnection of claim 1 wherein a current sense amplifiercircuit is coupled through a signal input node to the second end of saidtransmission line, said current sense amplifier comprising: a firsttransistor of a first conductivity type; a second transistor of a secondconductivity type, wherein the first and second transistors are coupledat a drain region; and said signal input node coupled to a source regionof the first transistor; and a signal output node coupled to the drainregion of the first and the second transistor in the second amplifier,and wherein the signal output node is further coupled to a gate of athird transistor.
 39. The integrated circuit interconnection of claim 38wherein a source region of the third transistor is coupled to a sourceregion of the second transistor, and wherein a drain region of the thirdtransistor is coupled to the signal input.
 40. The current senseamplifier of claim 38, wherein the first transistor of a firstconductivity type includes an n-channel metal oxide semiconductor (NMOS)transistor, and wherein the second transistor of a second conductivitytype includes a p-channel metal oxide semiconductor (PMOS) transistor.41. The current sense amplifier of claim 38, wherein the drain regionfor the first and the second transistor in the first amplifier arecoupled to gates of the second transistor in the first and the secondamplifier.
 42. The current sense amplifier of claim 38, wherein thethird transistor is an n-channel metal oxide semiconductor (NMOS)transistor.
 43. The current sense amplifier of claim 38, wherein thesignal input node of the first amplifier receives an input current, andwherein the signal input node of the second amplifier receives areference current.
 44. An integrated circuit interconnection forminimizing clock skews comprising: a transmission line having a lowcharacteristic impedance, said transmission line including a first endand a second end; a driver coupled to the first end of said transmissionline; a termination at the second end of said transmission line havingan impedance corresponding to the characteristic impedance of saidtransmission line for reducing ringing and reflections, said terminationincluding a current sense amplifier coupled to the second end of thetransmission line; and a plurality of components selected from the groupconsisting of capacitive elements, inductive elements and a combinationof capacitive and inductive elements, said components being connected atspaced intervals to said transmission line between said first and secondends for changing the propagation constant and delay time of saidtransmission line.
 45. The integrated circuit interconnection of claim44 wherein said components are a plurality of capacitive elements. 46.The integrated circuit interconnection of claim 44 wherein saidcomponents are a plurality of inductive elements.
 47. The integratedcircuit interconnection of claim 44 wherein said components are acombination of capacitive and inductive elements.
 48. The integratedcircuit interconnection of claim 44 wherein said transmission line has acharacteristic impedance of less than 50 Ohms.
 49. The integratedcircuit interconnection of claim 44 wherein a current sense amplifier iscoupled to the second end of the transmission line.
 50. The integratedcircuit interconnection of claim 44 wherein a plurality ofinterconnection lines are connected to said transmission line,
 51. Theintegrated circuit interconnection of claim 45 wherein said capacitiveelements are selected from the group consisting of metal-metal,metal-polysilicon and polysilicon-polysilicon capacitors.
 52. Theintegrated circuit interconnection of claim 45 wherein said capacitiveelements are gate capacitances of field effect transistors used ascapacitors.
 53. The integrated circuit interconnection of claim 46wherein said inductive elements are spiral inductors serially implantedin said transmission line.
 54. The integrated circuit interconnection ofclaim 46 wherein said inductive elements are formed by depositingmaterial with a higher magnetic permeability on said transmission linefor increasing self inductance of said transmission line.
 55. Theintegrated circuit interconnection of claim 49 wherein said currentsense amplifier which has an input impedance of less than 50 Ohms.
 56. Amethod for minimizing clock skews on integrated circuit interconnectionscomprising the steps of: providing a transmission line having a lowcharacteristic impedance, said transmission line including a first endand a second end; coupling a driver to the first end of saidtransmission line; coupling the second end of the transmission line to acurrent sense amplifier having an input impedance corresponding to thecharacteristic impedance of said transmission line for reducing ringingand reflections; and connecting a plurality components at spacedintervals to said transmission line between said first and second endsfor changing the propagation constant and delay time of saidtransmission line, said components being selected from the groupconsisting of capacitive elements, inductive elements and a combinationof capacitive and inductive elements.
 57. The method of claim 56 whereinsaid components are a plurality of capacitive elements.
 58. The methodof claim 56 wherein said components are a plurality of inductiveelements.
 59. The method of claim 56 wherein said components are acombination of capacitive and inductive elements.
 60. The method ofclaim 56 wherein said transmission line has a characteristic impedanceof less than 50 Ohms.
 61. The method of claim 56 further comprisingconnecting a plurality of interconnection lines to said transmissionline.
 62. The method of claim 57 wherein said capacitive elements areselected from the group consisting of metal-metal, metal-polysilicon andpolysilicon-polysilicon capacitors.
 63. The method of claim 57 whereinsaid capacitive elements are gate capacitances of field effecttransistors used as capacitors.
 64. The method of claim 58 wherein saidinductive elements are spiral inductors serially implanted in saidtransmission line.
 65. The method of claim 58 wherein said inductiveelements are formed by depositing material with a higher magneticpermeability on said transmission line for increasing self inductance ofsaid transmission line.
 66. The method of claim 56 wherein said currentsense amplifier which has an input impedance of less than 50 Ohms.